The present invention relates to a data output circuit for the semiconductor logic device and more particularly, it relates to a data output circuit having a plurality of output buffers through which logic data are output in parallel.
FIG. 1 shows the conventional data output circuit for n-bit logic data. The n-bit logic data are generated through the logic circuit formed in same IC package as the data output circuit, and supplied to data input terminals T1 - TN. This output circuit includes flip-flops 10-1 . . . 10-N for respectively holding logic signals applied from the data input terminals T1 - TN, and output buffers 12-1 . . . 12-N for transmitting outside the IC package the logic signals applied from the flip-flops 10-1 . . . 10-N. The output buffers 12-1 . . . 12-N have an even number of or, for example, two CMOS inverters connected in series, and the logic signals are transferred from the output buffers 12-1 . . . 12-N to input buffers 14-1 . . . 14-N of the external logic device through bus lines L1 - LN, respectively. The input buffers 14-1 - 14-N are substantially the same in construction as the output buffers 12-1 . . . 12-N, and the logic signals are supplied from the buffers 14-1 . . . 14-N to the optional logic circuit (not shown) through terminals R1 - RN. The bus lines L1 - LN have parasitic capacitances C1 - CN, respectively, relative to the ground; said parasitic capacitances C1 - CN ranging from 10 pF to 100 pF substantially. The power source line which serves to supply power from IC package pins to logic elements (e.g. output buffers 12-1 . . . 12-N) has an inductance of about 10 mH/cm.
When the logic data are re-newed, charge and discharge currents flow to and from the capacitors C1 - CN through the power source line, and noise voltage which prevents sudden current change is generated through the power source line. Particularly, when the logic data are re-newed from "000 . . . 0" to "111 . . . 1" or from "111 . . . 1" to "000 . . . 0", this noise voltage increases to erroneously operate the logic circuit in the IC package. This is the reason why the reliability relative to the integrated semiconductor logic device was low.